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? freescale semiconductor, inc., 2006. all rights reserved. ? preliminary freescale semiconductor data sheet: advance information MCF5208ec rev. 0.5, 3/2006 this document contains information on a new pr oduct. specifications and information herein are subject to change without notice. table of contents the mcf5207 and MCF5208 devices are highly-integrated 32-bit mi croprocessors based on the version 2 coldfire microarc hitecture. both devices contain a 16-kbyte intern al sram, an 8-kbyte configurable cache, a 2-bank sdr/ddr sdram controller, a 16-channel dma controller, up to three uarts, a queued spi, a low-power management modeule, and other periphera ls that enable the mcf5207 and MCF5208 for use in industrial control and connectivity appl ications. the MCF5208 device also features a 10/100 mbps fast ethernet controller. this document provides detailed information on power considerations, dc/ac electri cal characteristics, and ac timing specifications of the mcf5207 and MCF5208 microprocessors. it was writte n from the perspective of the MCF5208 device. see the following section for a summary of differences between the two devices. MCF5208 coldfire ? microprocessor data sheet supports mcf5207 & MCF5208 by: microcontroller division 1 mcf5207/8 device configurations......................2 2 ordering information ...........................................3 3 signal descriptions..............................................3 4 mechanicals and pinouts ....................................8 5 preliminary electrical characteristics................18 6 revision history ................................................43
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary mcf5207/8 device configurations freescale semiconductor 2 1 mcf5207/8 device configurations the following table compares the two devices described in this document: table 1. mcf5207 & MCF5208 configurations module mcf5207 MCF5208 version 2 coldfire core with emac (enhanced multiply-accumulate unit) xx core (system) clock up to 166.67 mhz peripheral and external bus clock (core clock 2) up to 83.33 mhz performance (dhrystone/2.1 mips) up to 159 instruction/data cache 8 kbytes static ram (sram) 16 kbytes sdr/ddr sdram controller x x fast ethernet controller (fec) ? x low-power management module x x uarts 3 3 i 2 cxx qspi x x 32-bit dma timers 4 4 watchdog timer (wdt) x x periodic interrupt timers (pit) 4 4 edge port module (eport) x x interrupt controllers (intc) 1 1 16-channel direct memory access (dma) x x flexbus external interface x x general purpose i/o module (gpio) x x jtag - ieee ? 1149.1 test access port x x package 144 lqfp 144 mapbga 160 qfp 196 mapbga
ordering information MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 3 2 ordering information 3 signal descriptions the following table lists all the MCF5208 pins grouped by function. th e ?dir? column is the direction for the primary function of the pin only. refer to section 4, ?mechanicals and pinouts,? for package diagrams. for a more detailed discussion of the MCF5208 signals, consult the MCF5208 reference manual (MCF5208rm). note in this table and throug hout this document a singl e signal within a group is designated without square brackets (i.e., a23), wh ile designations for multiple signals within a group use br ackets (i.e., a[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. note the primary functionality of a pin is not necessarily its de fault functionality. pins that are muxed with gpio will default to their gp io functionality. table 2. orderable part numbers freescale part number description speed temperature mcf5207cag166 mcf5207 risc microprocessor, 144 lqfp 166.67 mhz ?40 to +85 c mcf5207cvm166 mcf5207 risc microprocessor, 144 mapbga 166.67 mhz ?40 to +85 c MCF5208cab166 MCF5208 risc microprocessor, 160 qfp 166.67 mhz ?40 to +85 c MCF5208cvm166 MCF5208 risc microprocessor, 196 mapbga 166.67 mhz ?40 to +85 c table 3. mcf5207/8 signal information and muxing signal name gpio alternate 1 alternate 2 dir. 1 mcf5207 144 lqfp mcf5207 144 mapbga MCF5208 160 qfp MCF5208 196 mapbga reset reset 2 ? ? ? i 82 j10 90 j14 rstout ? ? ? o 74 m12 82 n14 clock extal ? ? ? i 78 k12 86 l14 xtal ? ? ? o 80 j12 88 k14 fb_clk ? ? ? o 34 l1 40 n1
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary signal descriptions freescale semiconductor 4 mode selection rcon 2 ? ? ? i 144 c4 160 c3 dramsel ? ? ? i 79 h10 87 k11 flexbus a[23:22] ? fb_cs [5:4] ? o 118, 117 b9, a10 126, 125 b11, a11 a[21:16] ? ? ? o 116?114, 112, 108, 107 c9, a11, b10, a12, c11, b11 124, 123, 122, 120, 116, 115 b12, a12, a13, b13, b14, c13 a[15:14] ? sd_ba[1:0] ? o 106, 105 b12, c12 114, 113 c14, d12 a[13:11] ? sd_a[13:11] ? o 104?102 d11, e10, d12 112, 111, 110 d13, d14, e11 a10 ? ? ? o 101 c10 109 e12 a[9:0] ? sd_a[9:0] ? o 100?91 e11, d9, e12, f10, f11, e9, f12, g10, g12, f9 108?99 e13, e14, f11?f14, g11?g14 d[31:16] ? sd_d[31:16] 3 ? o 21?28, 40?47 f1, f2, g1, g2, g4, g3, h1, h2, k3, l2, l3, k2, m3, j4, m4, k4 27?34, 46?53 j4?j1, k4?k1, m3, n3, m4, n4, p4, l5, m5, n5 d[15:0] ? fb_d[31:16] 3 ? o 8?15, 51?58 b2, b1, c2, c1, d2, d1, e2, e1, l5, k5, l6, j6, m6, j7, l7, k7 16?23, 57?64 f3?f1, g4?g1, h1, n6, p6, l7, m7, n7, p7, n8, p8 be/bwe [3:0] pbe[3:0] sd_dqm [3:0] ? o 20, 48, 18, 50 f4, l4, e3, j5 26, 54, 24, 56 h2, p5, h4, m6 oe pbusctl3 ? ? o 60 j8 66 m8 ta 2 pbusctl2 ? ? i 90 g11 98 h14 r/w pbusctl1? ?o59k665l8 ts pbusctl0 dack0 ?o 4 b3 12 e3 chip selects fb_cs [3:2] pcs[3:2] ? ? o 119, 120 d7, a9 ? c11, a10 fb_cs1 pcs1 sd_cs1 ? o 121 c8 127 b10 fb_cs0 ? ? ? o 122 b8 128 c10 table 3. mcf5207/8 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5207 144 lqfp mcf5207 144 mapbga MCF5208 160 qfp MCF5208 196 mapbga
signal descriptions MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 5 sdram controller sd_a10 ? ? ? o 37 m1 43 n2 sd_cke ? ? ? o 6 c3 14 e1 sd_clk ? ? ? o 31 j1 37 l1 sd_clk ? ? ? o 32 k1 38 m1 sd_cs0 ???o 7 a1 15 f4 sd_dqs[3:2] ? ? ? o 19, 49 f3, m5 25, 55 h3, l6 sd_scas ? ? ? o 38 m2 44 p2 sd_sras ? ? ? o 39 j2 45 p3 sd_sdr_dqs ? ? ? o 29 h3 35 l3 sd_we ???o5d313e2 external interrupts port 4 irq7 2 pirq7 2 ? ? i 134 a5 142 c7 irq4 2 pirq4 2 dreq0 2 ? i 133 c6 141 d7 irq1 2 pirq1 2 ? ? i 132 b6 140 d8 fec fec_mdc pfeci2c3 i2c_scl 2 u2txd o ? ? 148 d6 fec_mdio pfeci2c2 i2c_sda 2 u2rxd i/o ? ? 147 c6 fec_txclk pfech7 ? ? i ? ? 157 b3 fec_txen pfech6 ? ? o ? ? 158 a2 fec_txd0 pfech5 ? ? o ? ? 3 b1 fec_col pfech4 ? ? i ? ? 7 d3 fec_rxclk pfech3 ? ? i ? ? 154 b4 fec_rxdv pfech2 ? ? i ? ? 153 a4 fec_rxd0 pfech1 ? ? i ? ? 152 d5 fec_crs pfech0 ? ? i ? ? 8 d2 fec_txd[3:1] pfecl[7:5] ? ? o ? ? 6?4 c1, c2, b2 fec_txer pfecl4 ? ? o ? ? 156 a3 fec_rxd[3:1] pfecl[3:1] ? ? i ? ? 149?151 a5, b5, c5 fec_rxer pfecl0 ? ? i ? ? 155 c4 i 2 c i2c_sda 2 pfeci2c0 2 u2rxd 2 ? i/o ? ? ?d1 table 3. mcf5207/8 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5207 144 lqfp mcf5207 144 mapbga MCF5208 160 qfp MCF5208 196 mapbga
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary signal descriptions freescale semiconductor 6 i2c_scl 2 pfeci2c1 2 u2txd 2 ? i/o ? ? ?e4 dma dack0 and dreq0 do not have a dedicated bond pads. please refer to the following pins for muxing: ts and qspi_cs2 for dack0 , irq4 and qspi_din for dreq0 . qspi qspi_cs2 pqspi3 dack0 u2rts o 126 a8 132 d10 qspi_clk pqspi0 i2c_scl 2 ? o 127 c7 133 a9 qspi_dout pqspi1 i2c_sda 2 ? o 128 a7 134 b9 qspi_din pqspi2 dreq0 2 u2cts i 129 b7 135 c9 note: the qspi_cs1 and qspi_cs0 signals are available on the u1cts , u1rts , u0cts , or u0rts pins for the 196 and 160-pin packages. uarts u1cts puartl7 ? ? i 139 b4 ? ? u1rts puartl6 ? ? o 142 a2 ? ? u1cts puartl7 dt1in qspi_cs1 i ? ? 136 d9 u1rts puartl6 dt1out qspi_cs1 o ? ? 137 c8 u1txd puartl5 ? ? o 131 a6 139 a8 u1rxd puartl4 ? ? i 130 d6 138 b8 u0cts puartl3 ? ? i 140 e4 ? ? u0rts puartl2 ? ? o 141 d5 ? ? u0cts puartl3 dt0in qspi_cs0 i ? ?76n12 u0rts puartl2 dt0out qspi_cs0 o ? ?77p12 u0txd puartl1 ? ? o 71 l10 79 p13 u0rxd puartl0 ? ? i 70 m10 78 n13 note: the uart2 signals are multiplexed on the dma timers, qspi, fec, and i2c pins. dma timers dt3in ptimer3 dt3out u2cts i 135 b5 143 b7 dt2in ptimer2 dt2out u2rts i 136 c5 144 a7 dt1in ptimer1 dt1out u2rxd i 137 a4 145 a6 dt0in ptimer0 dt0out u2txd i 138 a3 146 b6 bdm/jtag 5 jtag_en 6 ? ? ? i 83 j1191j13 dsclk ? trst 2 ? i 76 k11 84 l12 table 3. mcf5207/8 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5207 144 lqfp mcf5207 144 mapbga MCF5208 160 qfp MCF5208 196 mapbga
signal descriptions MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 7 pstclk ? tclk 2 ? o 64 m7 70 p9 bkpt ? tms 2 ? i 75 l12 83 m14 dsi ? tdi 2 ? i 77 h9 85 k12 dso ? tdo ? o 69 m9 75 m12 ddata[3:0] ? ? ? o ? k9, l9, m11, m8 ?p11, n11, m11, p10 pst[3:0] ? ? ? o ? l11, l8, k10, k8 ? n10, m10, l10, l9 allpst ? ? ? o 67 ? 73 ? test test 6 ? ? ? i 109 ??c12 pll_test ? ? ? i ? ??m13 power supplies evdd ? ? ? 1, 63, 66, 72, 81, 87, 125 e5?e6, f5, g8?g9, h7?h8 2, 9, 69, 72, 80, 89, 95, 131 e5?e7, f5, f6, g5, h10, j9, j10, k8?k10, k13, m9 ivdd ? ? ? 30, 68, 84, 113, 143 d4, d8, h4, h11, j9 36, 74, 92, 121, 159 j12, d4, d11, h11, l4, l11, pll_vdd ? ? ? 86 h12 94 h13 sd_vdd ? ? ? 3, 17, 33, 35, 61, 89, 110, 123 e7?e8, f8, g5, h5?h6, j3 11, 39, 41, 67, 97, 118, 129 e8?e10, f9, f10, g10, h5, j5, j6, k5?k7, l2 vss ? ? ? 2, 16, 36, 62, 65, 73, 88, 111, 124 d10, f6?f7, g6?g7 1, 10, 42, 68, 71, 81, 96, 117, 119, 130 a1, a14, f7?f8, g6?g9, h6?h9, j7?j8, l13, m2, n9, p1, p14 pll_vss ? ? ? 85 ?93h12 notes: 1 refers to pin?s primary function. 2 pull-up enabled internally on this signal for this mode. 3 primary functionality selected by asserting the dramsel sig nal (sdr mode). alternate functionality selected by negating the dramsel signal (ddr mode). the gpio module is not responsible for assigning these pins. 4 gpio functionality is determined by the edge port module. the gp io module is only responsible for assigning the alternate functions. table 3. mcf5207/8 signal information and muxing (continued) signal name gpio alternate 1 alternate 2 dir. 1 mcf5207 144 lqfp mcf5207 144 mapbga MCF5208 160 qfp MCF5208 196 mapbga
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary mechanicals and pinouts freescale semiconductor 8 4 mechanicals and pinouts this section contains drawings s howing the pinout and the packaging a nd mechanical char acteristics of the mcf5207 and MCF5208 devices. note the mechanical drawings are the latest revisions at the time of publication of this document. the most up-to-date mechanical drawings can be found at the product summary page located at http://www.freescale.com/coldfire . 5 if jtag_en is asserted, these pins default to alternate 1 (jtag) functionality. the gpio module is not responsible for assigning these pins. 6 pull-down enabled internally on this signal for this mode.
mechanicals and pinouts MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 9 4.1 pinout?144 lqfp figure 1 shows a pinout of the mcf5207cag166 device. figure 1. mcf5207cag166 pinout top view (144 lqfp) rcon ivdd u1rts u0rts u0cts u1cts dt0in dt1in dt2in dt3in irq7 irq4 irq1 u1txd u1rxd qspi_din qspi_dout qspi_clk qspi_cs2 evdd vss sd_vdd fb_cs0 fb_cs1 fb_cs2 fb_cs3 a23 a22 a21 a20 a19 ivdd a18 vss sd_vdd test 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 evdd 1 108 a17 evss 2 107 a16 sd_vdd 3 106 a15 ts 4 105 a14 sd_we 5 104 a13 sd_cke 6 103 a12 sd_cs 7 102 a11 d15 8 101 a10 d14 9 100 a9 d13 10 99 a8 d12 11 98 a7 d11 12 97 a6 d10 13 96 a5 d9 14 95 a4 d8 15 94 a3 evss 16 93 a2 sd_vdd 17 92 a1 be/bwe1 18 91 a0 sd_dqs1/3 19 90 ta be/bwe3 20 89 sd_vdd d31 21 88 vss d30 22 87 evdd d29 23 86 pll_vdd d28 24 85 pll_vss d27 25 84 ivdd d26 26 83 jtag_en d25 27 82 reset d24 28 81 evdd sd_sdr_dqs 29 80 xtal ivdd 30 79 dramsel sd_clk 31 78 extal sd_clk 32 77 tdi/dsi sd_vdd 33 76 trst /dsclk fb_clk 34 75 tms/bkpt sd_vdd 35 74 rstout vss 36 73 vss 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 sd_a10 sd_cas sd_ras d23 d22 d21 d20 d19 d18 d17 d16 be/bwe2 sd_dqs0/2 be/bwe0 d7 d6 d5 d4 d3 d2 d1 d0 r/w oe sd_vdd vss evdd tclk/pstclk vss evdd all_pst ivdd tdo/dso u0rxd u0txd evdd
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary mechanicals and pinouts freescale semiconductor 10 4.2 package dimensions?144 lqfp figure 2 and figure 3 show mcf5207cab166 package dimensions. figure 2. mcf5207cab166 package dimensions (sheet 1 of 2)
mechanicals and pinouts MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 11 figure 3. mcf5207cab166 package dimensions (sheet 2 of 2) view a section a-a rotated 90 cw 144 places view b
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary mechanicals and pinouts freescale semiconductor 12 4.3 pinout?144 mapbga the pinout of the mcf5207cvm166 device is shown below. 123456789101112 asd_cs u1rts dt0in dt1in irq7 u1txd qspi_ dout qspi_cs2 fb_cs2 a22 a20 a18 a b d14 d15 ts u1cts dt3in irq1 qspi_din fb_cs0 a23 a19 a16 a15 b c d12 d13 sd_cke rcon dt2in irq4 qspi_ clk fb_cs1 a21 a10 a17 a14 c d d10 d11 sd_we ivdd u0rts u1rxd fb_cs3 ivdd a8 vss a13 a11 d e d8 d9 be/bwe1 u0cts evdd evdd sd_vdd sd_vdd a4 a12 a9 a7 e f d31 d30 sd_dqs1 be/bwe3 evdd vss vss sd_vdd a0 a6 a5 a3 f g d29 d28 d26 d27 sd_vdd vss vss evdd evdd a2 ta a1 g h d25 d24 sd_sdr_ dqs ivdd sd_vdd sd_vdd evdd evdd tdi/dsi dram sel ivdd pll_vdd h j sd_clk sd_ras sd_vdd d18 be/bwe0 d4 d2 oe ivdd reset jtag_en xtal j k sd_clk d20 d23 d16 d6 r/w d0 pst0 ddata3 pst1 trst / dsclk extal k lfb_clk d22 d21 be/bwe2 d7 d5 d1 pst2 ddata2 u0txd pst3 tms/ bkpt l m sd_a10 sd_cas d19 d17 sd_dqs0 d3 tclk/ pstclk ddata0 tdo/dso u0rxd ddata1 rstout m 123456789101112 figure 4. mcf5207cvm166 pinout top view (144 mapbga)
mechanicals and pinouts MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 13 4.4 package dimensions?144 mapbga figure 5 shows the mcf5207cab166 package dimensions. figure 5. mcf5207cab166 package dimensions (144 mapbga)
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary mechanicals and pinouts freescale semiconductor 14 4.5 pinout?160 qfp figure 6 shows a pinout of the MCF5208cab166 device. figure 6. MCF5208cab166 pinout top view (160 qfp) rcon ivdd fec_txen fec_txclk fec_txer fec_rxer fec_rxclk fec_rxdv fec_rxd0 fec_rxd1 fec_rxd2 fec_rxd3 fec_mdc fec_mdio dt0in dt1in dt2in dt3in irq7 irq4 irq1 u1txd u1rxd u1rts u1cts qspi_din qspi_dout qspi_clk qspi_cs2 evdd vss sd_vdd fb_cs0 fb_cs1 a23 a22 a21 a20 a19 ivdd 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 vss 1 120 a18 evdd 2 119 vss fec_txd0 3 118 sd_vdd fec_txd1 4 117 vss fec_txd2 5 116 a17 fec_txd3 6 115 a16 fec_col 7 114 a15 fec_crs 8 113 a14 evdd 9 112 a13 vss 10 111 a12 sd_vdd 11 110 a11 ts 12 109 a10 sd_we 13 108 a9 sd_cke 14 107 a8 sd_cs 15 106 a7 d15 16 105 a6 d14 17 104 a5 d13 18 103 a4 d12 19 102 a3 d11 20 101 a2 d10 21 100 a1 d9 22 99 a0 d8 23 98 ta be/bwe1 24 97 sd_vdd sd_dqs1/3 25 96 vss be/bwe3 26 95 evdd d31 27 94 pll_vdd d30 28 93 pll_vss d29 29 92 ivdd d28 30 91 jtag_en d27 31 90 reset d26 32 89 evdd d25 33 88 xtal d24 34 87 dramsel sd_sdr_dqs 35 86 extal ivdd 36 85 tdi/dsi sd_clk 37 84 trst /dsclk sd_clk 38 83 tms/bkpt sd_vdd 39 82 rstout fb_clk 40 81 vss 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 sd_vdd vss sd_a10 sd_cas sd_ras d23 d22 d21 d20 d19 d18 d17 d16 be/bwe2 sd_dqs0/2 be/bwe0 d7 d6 d5 d4 d3 d2 d1 d0 r/w oe sd_vdd vss evdd tclk/pstclk vss evdd all_pst ivdd tdo/dso u0cts u0rts u0rxd u0txd evdd
mechanicals and pinouts MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 15 4.6 package dimensions?160 qfp the package dimensions of the MCF5208cab166 device are shown in the figures below. figure 7. MCF5208cab166 package dimensions (sheet 1 of 2) top view
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary mechanicals and pinouts freescale semiconductor 16 figure 8. MCF5208cab166 package dimensions (sheet 2 of 2) detail a section b-b
mechanicals and pinouts MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 17 4.7 pinout?196 mapbga figure 6 shows a pinout of the MCF5208cvm166 device. 1234567891011121314 a vss fec_ txen fec_ txer fec_ rxdv fec_ rxd3 dt1in dt2in u1txd qspi_ clk fb_cs2 a22 a20 a19 vss a b fec_ txd0 fec_ txd1 fec_ txclk fec_ rxclk fec_ rxd2 dt0in dt3in u1rxd qspi_ dout fb_cs1 a23 a21 a18 a17 b c fec_ txd3 fec_ txd2 rcon fec_ rxer fec_ rxd1 fec_ mdio irq7 u1rts qspi_ din fb_cs0 fb_cs3 test a16 a15 c d i2c_sda fec_ crs fec_ col ivdd fec_ rxd0 fec_ mdc irq4 irq1 u1cts qspi_ cs2 ivdd a14 a13 a12 d e sd_cke sd_we ts i2c_scl evdd evdd evdd sd_vdd sd_vdd sd_vdd a11 a10 a9 a8 e f d13 d14 d15 sd_cs evdd evdd vss vss sd_vdd sd_vdd a7 a6 a5 a4 f g d9 d10 d11 d12 evdd vss vss vss vss sd_vdd a3 a2 a1 a0 g h d8 be/ bwe3 sd_ dqs1 be/ bwe1 sd_vdd vss vss vss vss evdd ivdd pll_ vss pll_ vdd ta h j d28 d29 d30 d31 sd_vdd sd_vdd vss vss evdd evdd nc ivdd jtag_ en reset j k d24 d25 d26 d27 sd_vdd sd_vdd sd_vdd evdd evdd evdd dram sel tdi/ dsi evdd xtal k l sd_clk sd_vdd sd_dr_ dqs ivdd d18 sd_ dqs0 d5 r/w pst0 pst1 ivdd trst / dsclk vss extal l m sd_clk vss d23 d21 d17 be/ bwe0 d4 oe evdd pst2 ddata1 tdo/ dso pll_ test tms/ bkpt m nfb_clksd_a10 d22 d20 d16 d7 d3 d1 vss pst3 ddata2 u0cts u0rxd rstout n p vss sd_cas sd_ras d19 be/ bwe2 d6 d2 d0 tclk/ pstclk ddata0 ddata3 u0rts u0txd vss p 1234567891011121314 figure 9. MCF5208cvm166 pinout top view (196 mapbga)
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 18 4.8 package dimensions?196 mapbga the package dimensions for the mc f5208cvm166 device is shown below. figure 10. MCF5208cvm166 package dimensions (196 mapbga) 5 preliminary electrical characteristics the following electrical specifica tions are preliminary and are fr om previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for produc tion silicon these specificati ons will be met. finalize d specifications will be published after complete characterization and device qualifications have been completed. 5.1 maximum ratings table 4. absolute maximum ratings 1, 2 rating symbol value unit core supply voltage iv dd ? 0.5 to +2.0 v cmos pad supply voltage ev dd ? 0.3 to +4.0 v ddr/memory pad supply voltage sdv dd ? 0.3 to +4.0 v pll supply voltage pllv dd ? 0.3 to +2.0 v top view bottom view
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 19 5.2 thermal characteristics table 5 lists thermal resistance values digital input voltage 3 v in ? 0.3 to +3.6 v instantaneous maximum current single pin limit (applies to all pins) 3, 4, 5 i d 25 ma operating temperature range (packaged) t a (t l - t h ) ? 40 to 85 c storage temperature range t stg ? 55 to 150 c notes: 1 functional operating conditions are given in section 5.4, ?dc electrical specifications.? absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. continued operation at these le vels may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting a gainst damage due to high static voltage or electrical fields; however, it is advised that no rmal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or ev dd ). 3 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 all functional non-supply pins are internally clamped to v ss and ev dd . 5 power supply must maintain regulation within operating ev dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > ev dd is greater than i dd , the injection current may flow out of ev dd and could result in external power supply going out of regulation . insure external ev dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power (ex; no clock). power supply must maintain regulation within operating ev dd range during instantaneous and operating maximum current conditions. table 5. thermal characteristics characteristic symbol 196mbga 160qfp unit junction to ambient, natural convection four layer board (2s2p) jma 32 1,2 40 1,2 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 29 1,2 36 1,2 c / w junction to board jb 20 3 25 3 c / w junction to case jc 10 4 10 4 c / w junction to top of package jt 2 1,5 2 1,5 c / w maximum operating junction temperature t j 105 105 o c table 4. absolute maximum ratings 1, 2 (continued)
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 20 the average chip-junction temperature (t j ) in c can be obtained from: eqn. 1 where: t a = ambient temperature, c q jma = package thermal resistance, junction-to-ambient, c/w p d =p int + p i/o p int =i dd iv dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an appr oximate relationship between p d and t j (if p i/o is neglected) is: eqn. 2 solving equations 1 and 2 for k gives: eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 5.3 esd protection notes: 1 jma and jt parameters are simulated in conformance with eia/jesd standard 51-2 for natural convection. freescale recommends the use of jma and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. system design ers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. conformance to the device junction temperature specif ication can be verified by physical measurement in the customer?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. 3 thermal resistance between the die and the printed circuit board in conformance with jedec jesd51-8. board temperature is measured on the top su rface of the board near the package. 4 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 5 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written in conformance with psi-jt. table 6. esd protection characteristics 1, 2 characteristics s ymbol value units esd target for human body model hbm 2000 v t j t a p d jma () + = p d k t j 273 c + () -------------------------------- - = kp d t a 273 c () q jma p d 2 + =
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 21 5.4 dc electrical specifications notes: 1 all esd testing is in conformity with cdf -aec-q100 stress test qualification for automotive grade integrated circuits. 2 a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. comple te dc parametric and functional testing is performed per applicable device specificat ion at room temperature followed by hot temperature, unless specified otherwi se in the device specification. table 7. dc electrical specifications characteristic symbol min max unit core supply voltage iv dd 1.4 1.6 v pll supply voltage pllv dd 1.4 1.6 v cmos pad supply voltage ev dd 3.0 3.6 v mobile ddr/bus pad supply voltage sdv dd 1.65 1.95 v ddr/bus pad supply voltage sdv dd 2.25 2.75 v sdr/bus pad supply voltage sdv dd 3.0 3.6 v cmos input high voltage ev ih 2ev dd +0.05 v cmos input low voltage ev il -0.05 0.8 v mobile ddr/bus input high voltage sdv ih tbd sdv dd +0. 05 v mobile ddr/bus input low voltage sdv il -0.05 tbd v ddr/bus input high voltage sdv ih 2sdv dd +0. 05 v ddr/bus input low voltage sdv il -0.05 0.8 v input leakage current v in = iv dd or v ss , input-only pins i in ?1.0 1.0 a cmos output high voltage i oh = ?5.0 ma ev oh ev dd - 0.4 ? v cmos output low voltage i ol = 5.0 ma ev ol ?0.4v ddr/bus output high voltage i oh = ?5.0 ma sdv oh sdv dd - 0.4 ? v ddr/bus output low voltage i ol = 5.0 ma sdv ol ?0.4v weak internal pull up device current, tested at v il max. 1 i apu -10 - 130 a
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 22 5.4.1 pll power filtering to further enhance noise isolation, an external filter is strongly reco mmended for pll analog v dd pins. the filter shown in figure 11 should be connected between the board v dd and the pllv dd pins. the resistor and capacitors should be pl aced as close to the dedicated pllv dd pin as possible. figure 11. system pll v dd power filter 5.4.2 supply voltage sequencing and separation cautions figure 12 shows situations in sequencing the i/o v dd (ev dd ), sdram v dd (sdv dd ), pll v dd (pllv dd ), and core v dd (iv dd ). input capacitance 2 all input-only pins all input/output (t hree-state) pins c in ? ? 7 7 pf core operating supply current 3 master mode limp mode stop mode low power mode i dd ?170 tbd 1 tbd ma ma ma ma notes: 1 refer to the signals section for pins having weak internal pull-up devices. 2 this parameter is characterized before qualification rather than 100% tested. 3 current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. table 7. dc electrical specifications (continued) characteristic symbol min max unit board v dd 10 ? 0.1 f pll v dd pin 10 f gnd
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 23 figure 12. supply voltage sequencing and separation cautions the relationship between sdv dd and ev dd is non-critical during power- up and power-down sequences. both sdv dd (2.5v or 3.3v) and ev dd are specified relative to iv dd . 5.4.2.1 power up sequence if ev dd /sdv dd are powered up with iv dd at 0 v, then the sense circuits in the i/o pads will cause all pad output drivers connected to the ev dd /sdv dd to be in a high impedance state. there is no limit on how long after ev dd /sdv dd powers up before iv dd must powered up. iv dd should not lead the ev dd , sdv dd or pllv dd by more than 0.4 v during power ramp-up, or th ere will be high current in the internal esd protection diodes. the ri se times on the power supplie s should be slower than 1 s to avoid turning on the internal esd protection clamp diodes. the recommended power up sequence is as follows: 1. use 1 s or slower rise time for all supplies. 2. iv dd /pllv dd and ev dd /sdv dd should track up to 0.9 v, then separate for the completion of ramps with ev dd /sd v dd going to the higher external voltages. one way to accomplish this is to use a low drop-out voltage regulator. 5.4.2.2 power down sequence if iv dd /pllv dd are powered down first, then sense circuits in the i/o pads will cause all output drivers to be in a high impedance state. there is no limit on how long after iv dd and pllv dd power down before ev dd or sdv dd must power down. iv dd should not lag ev dd , sdv dd , or pllv dd going low by more sdv dd (2.5v/1.8v) supplies stable 2 1 3.3v 2.5v 1.5v 0 time notes: iv dd should not exceed ev dd , sdv dd or pllv dd by more than 0.4 v at any time, including power-up. recommended that iv dd /pllv dd should track ev dd /sdv dd up to 0.9 v, then separate for completion of ramps. input voltage must not be greater than the supply voltage (ev dd , sdv dd , iv dd , or pllv dd ) by more than 0.5 v at any time, including during power-up. use 1 s or slower rise time for all supplies. 1. 2. 3. 4. dc power supply voltage iv dd , pllv dd ev dd , sdv dd
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 24 than 0.4 v during power down or there will be undesi red high current in the esd protection diodes. there are no requirements for the fall times of the power supplies. the recommended power down sequence is as follows: 1. drop iv dd /pllv dd to 0 v. 2. drop ev dd /sdv dd supplies. 5.5 oscillator and pll electrical characteristics 5.6 external interface timing characteristics table 9 lists processor bus input timings. note all processor bus timings are synchr onous; that is, input setup/hold and output delay with respect to the ri sing edge of a reference clock. the reference clock is the fb_clk output. all other timing relations hips can be derived from these values.timings listed in table 9 are shown in figure 14 & figure 15 . table 8. pll electrical characteristics num characteristic symbol min. value max. value unit 1 pll reference frequency range crystal reference external reference f ref_crystal f ref_ext tbd tbd 16 16 mhz mhz 2 core frequency clkout frequency 1 notes: 1 all internal registers retain data at 0 hz. f sys f sys/2 tbd tbd 166.67 83.33 mhz mhz 3 crystal start-up time 2, 3 2 this parameter is guaranteed by characteriza tion before qualification rather than 100% tested. 3 proper pc board layout procedures must be followed to achieve specifications. t cst ?10ms 4 extal input high voltage crystal mode 4 all other modes (e xternal, limp) 4 this parameter is guaranteed by design rather than 100% tested. v ihext v ihext tbd tbd tbd tbd v v 5 extal input low voltage crystal mode 4 all other modes (e xternal, limp) v ilext v ilext tbd tbd tbd tbd v v 6 xtal load capacitance 2 530pf 11 pll lock time 2,5 t lpll ?1 ms 14 duty cycle of reference 2 t dc 40 60 %
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 25 figure 13. general input timing requirements 5.6.1 flexbus a multi-function external bus interf ace called flexbus is provided to inte rface to slave-onl y devices up to a maximum bus frequency of 83.33 mhz. it can be directly connected to asynchronous or synchronous devices such as external boot roms, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. for asynchronous device s a simple chip-sel ect based interface can be used. the flexbus interface has six general purpose chip-selects (fb_cs [5:0]) which can be configured to be distributed between the flexbu s or sdram memory interfaces. chip-select fb_cs [0] can be dedicated to boot rom access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. control signal timing is compatible wi th common rom/flash memories. 5.6.1.1 flexbus ac timing characteristics the following timing numbers i ndicate when data will be latched or driven onto the external bus, relative to the system clock. table 9. flexbus ac timing specifications num characteristic symbol min max unit notes frequency of operation 83.33 mhz f sys/2 fb1 clock period (fb_clk) t fbck 12 ns t cyc invalid invalid fb_clk(75mhz) t setup t hold input setup and hold 1.5v t rise v h = v ih v l = v il 1.5v 1.5v valid t fall v h = v ih v l = v il input rise time input fall time * the timings are also valid for inputs sampled on the negative clock edge. inputs fb_clk fb4 fb5
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 26 figure 14. flexbus read timing fb2 data, and control output valid (a[23:0], d[31:0], fb_cs [5:0], r/w , ts , be/bwe [3:0] and oe ) t fbchdcv ?7.0 ns 1 fb3 data, and control output hold ((a[23:0], d[31:0], fb_cs [5:0], r/w , ts , be/bwe [3:0], and oe ) t fbchdci 1? ns 1 , 2 fb4 data input setup t dvfbch 3.5 ? ns fb5 data input hold t difbch 0? ns fb6 transfer acknowledge (t a ) input setup t cvfbch 4? ns fb7 transfer acknowledge (t a ) input hold t cifbch 0? ns fb8 address output valid (a[23:0]) t fbchav ?6.0 ns 3 fb9 address output hold (a[23:0]) t fbchai 1.0 ? ns notes: 1 timing for chip selects only applies to the fb_cs [5:0] signals. please see section 5.7 , "sdram bus? for sd_cs [1:0] timing. 2 the flexbus supports programming an extension of the addre ss hold. please consult the device reference manual for more information. 3 these specs are used when the a[23:0] signals are configured as 23-bit, non-muxed flexbus address signals. table 9. flexbus ac timing specifications num characteristic symbol min max unit notes fb_clk a[23:0] d[31:0] r/w t s fb_cs n , be/bwe n o e ta fb1 a[23:0] fb2 fb9 fb4 fb5 fb6 fb7 data fb8
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 27 figure 15. flexbus write timing 5.7 sdram bus the sdram controller supports acces ses to main sdram memory from any internal master. it supports either standard sdram or double data rate (ddr) sdram, but it does not support both at the same time. the sdram controller uses sstl2 and sstl3 i/o drivers. both sstl driv e modes are programmable for either class i or class ii drive strength. 5.7.1 sdr sdram ac timing characteristics the following timing numbers i ndicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when oper ating in sdr mode on wr ite cycles and relative to sd_dqs on read cycles. the sdram controller is a ddr controller th at has an sdr mode. beca use it is designed to support ddr, a dqs pulse must still be supplied to th e device for each data beat of an sdr read. the coldfire processor accomplishes this by asserting a signal ca lled sd_dqs during read cycles. care must be taken during board design to adhe re to the following guidelines and specs with regard to the sdr_dqs signal and its usage. fb_clk a[23:0] d[31:0] r/w t s fb_cs n , be/bwe n t a fb1 fb2 fb9 fb3 fb6 fb7 o e fb8
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 28 table 10. sdr timing specifications symbol characteristic symbol min max unit notes frequency of operation ? 83.33 mhz 1 notes: 1 the device supports the same frequency of operation for both flexbus and sdram as that of the internal bus clock. please see the pll chapter of the MCF5208 reference manual for more information on setting the sdram clock rate. sd1 clock period (t ck )t sdck 7.52 12 ns 2 2 sd_clk is one sdram clock in (ns). sd2 clock skew (t sk )t sdsk ?tbd sd3 pulse width high (t ckh )t sdckh 0.45 0.55 sd_clk 3 3 pulse width high plus pulse width low cannot exceed min and max clock period. sd4 pulse width low (t ckl )t sdckl 0.45 0.55 sd_clk 3 sd5 address, sd_cke, sd_cas , sd_ras , sd_we , sd_ba, sd_cs [1:0] - output valid (t cmv ) t sdchacv ?0.5 sd_clk +1.0 ns sd6 address, sd_cke, sd_cas , sd_ras , sd_we , sd_ba, sd_cs [1:0] - output hold (t cmh ) t sdchaci 2.0 ? ns sd7 sd_sdr_dqs output valid (t dqsov )t dqsov ?self timedns 4 4 sd_dqs is designed to pulse 0.25 clock before the rising edge of t he memory clock. this is a guideline only. subtle variation f rom this guideline is expected. sd_dqs will only pulse during a read cycle and one pulse will occur for each data beat. sd8 sd_dqs[3:0] input setup relative to sd_clk (t dqsis )t dqvsdch 0.25 sd_clk 0.40 sd_clk ns 5 5 sdr_dqs is designed to pulse 0.25 clock before the rising edge of the memory clock. this spec is a guideline only. subtle variation from this guideline is expected. sdr_dqs will only pulse during a read cycle and one pulse will occur for each data b eat. sd9 sd_dqs[3:2] input hold relative to sd_clk (t dqsih )t dqisdch does not apply. 0.5 sd_clk fixed width. 6 6 the sdr_dqs pulse is designed to be 0.5 clock in width. the ti ming of the rising edge is most important. the falling edge does not affect the memory controller. sd10 data (d[31:0]) input setup relative to sd_clk (reference only) (t dis ) t dvsdch 0.25 sd_clk ? ns 7 7 since a read cycle in sdr mode still uses th e dqs circuit within the device, it is mo st critical that t he data valid window be centered 1/4 clk after the rising edge of dqs. ensuring that this happens will result in successful sdr r eads. the input setup spec is j ust provided as guidance. sd11 data input hold relative to sd_clk (reference only) (t dih ) t disdch 1.0 ? ns sd12 data (d[31:0]) and data mask(sd_dqm[3:0]) output valid (t dv ) t sdchdmv ?0.75 sd_clk + 0.5 ns sd13 data (d[31:0]) and data mask (sd_dqm[3:0]) output hold (t dh ) t sdchdmi 1.5 ? ns
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 29 figure 16. sdr write timing sd_clk0 sd_clk1 sddm d[31:0] a[23:0], sd_ba[1:0] sd2 cmd row sd2 sd1 sd5 col sd6 wd1 wd2 wd3 wd4 sd13 sd12 sd3 sd4 sd_csn , sd_ras , sd_we , sd_cas
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 30 figure 17. sdr read timing 5.7.2 ddr sdram ac timing characteristics when using the sdram controller in ddr mode, th e following timing numbers must be followed to properly latch or drive data onto th e memory bus. all timing numbers ar e relative to the four dqs byte lanes. the following timing numbers ar e subject to change at anytime, a nd are only provided to aid in early board design. please contact your local freesca le representative if questions develop. table 11. ddr timi ng specifications num characteristic symbol min max unit notes frequency of operation 83.33 tbd mhz 1 dd1 clock period (sd_clk) t ddck tbd 12 ns 2 dd2 pulse width high t ddckh 0.45 0.55 sd_clk 3 dd3 pulse width low t ddckl 0.45 0.55 sd_clk 3 dd4 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] - output valid t sdchacv ?0.5 sd_clk +1.0 ns 4 sd_clk0 sd_clk1 sd_csn , sddm d[31:0] a[23:0], sd_ras , sd_ba[1:0] sd2 cmd row sd2 sd1 sd5 col wd1 wd2 wd3 wd4 sd10 3/4 mclk sd_dqs sd_ddqs delayed sd11 sd8 board delay sd9 board delay sd7 tdqs reference sd_clk form memories (measured at output pin) (measured at input pin) sd6 note: data driven from memories relative to delayed memory clock. sd_we sd_cas ,
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 31 dd5 address, sd_cke, sd_cas , sd_ras , sd_we , sd_cs [1:0] - output hold t sdchaci 2.0 ? ns dd6 write command to first dqs latching transition t cmdvdq 1.25 sd_clk dd7 data and data mask output setup (dq-->dqs) relative to dqs (ddr write mode) t dqdmv 1.5 ? ns 5 6 dd8 data and data mask output hold (dqs-->dq) relative to dqs (ddr write mode) t dqdmi 1.0 ? ns 7 dd9 input data skew relative to dqs (input setup) t dvdq ?1ns 8 dd10 input data hold relative to dqs. t didq 0.25 sd_clk +0.5ns ?ns 9 dd11 dqs falling edge from sdclk rising (output hold time) t dqlsdch 0.5 ? ns dd12 dqs input read preamble width (t rpre )t dqrpre 0.9 1.1 sd_clk dd13 dqs input read postamble width (t rpst )t dqrpst 0.4 0.6 sd_clk dd14 dqs output write preamble width (t wpre )t dqwpre 0.25 ? sd_clk dd15 dqs output write postamble width (t wpst )t dqwpst 0.4 0.6 sd_clk notes: 1 the frequency of operation is either 2x or 4x the fb_clk frequency of operation. fl exbus and sdram clock operate at the same frequency as the internal bus clock. 2 sd_clk is one sdram clock in (ns). 3 pulse width high plus pulse width low cannot exceed min and max clock period. 4 command output valid should be 1/2 the memory bus clock (sd_clk) plus some minor adjustments for process, temperature, and voltage variations. 5 this specification relates to the required input setup time of today?s ddr memories. the device?s output setup should be larger than the input setup of the ddr memories. if it is not larger , then the input setup on the memory will be in violation. mem_data[31:24] is relative to mem_dqs[ 3], mem_data[23:16] is relative to mem_ dqs[2], mem_data[15:8] is relative to mem_dqs[1], and mem_[7:0] is relative mem_dqs[0]. 6 the first data beat will be valid before the first rising edge of dqs and after the dqs write preamble. the remaining data beat s will be valid for each subsequent dqs edge. 7 this specification relates to the required hold time of today?s ddr memories. mem_ data[31:24] is relative to mem_dqs[3], mem_data[23:16] is relative to mem_dq s[2], mem_data[15:8] is relative to mem_dqs[1], and mem_[7:0] is relative mem_dqs[0]. 8 data input skew is derived from each dqs clock edge. it begi ns with a dqs transition and end s when the last data line becomes valid. this input skew must include ddr memory output skew and system level board skew (due to routing or other factors). 9 data input hold is derived from each dqs clock edge. it begins with a dqs transition and ends when the first data line becomes invalid. table 11. ddr timing specifications (continued) num characteristic symbol min max unit notes
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 32 figure 18. ddr write timing sd_clk sd_cs n , sd_we , dm3/dm2 d[31:24]/d[23:16] a[13:0] sd_ras , sd_ cas cmd row dd1 dd5 dd4 col wd1 wd2 wd3 wd4 dd7 sd_dqs3/sd_dqs2 dd8 dd8 dd7 sd_clk dd3 dd2 dd6
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 33 figure 19. ddr read timing figure 20 shows the ddr clock cr ossover specifications. figure 20. ddr clock crossover timing 5.8 general purpose i/o timing table 12. gpio timing 1 num characteristic symbol min max unit g1 fb_clk high to gpio output valid t chpov ?8ns g2 fb_clk high to gpio output invalid t chpoi 1.5 ? ns g3 gpio input valid to fb_clk high t pvch 8?ns g4 fb_clk high to gpio input invalid t chpi 1.5 ? ns sd_clk sd_cs n , sd_we , sd_dqs3/sd_dqs2 d[31:24]/d[23:16] a[13:0] sd_ras , sd_cas cmd row dd1 dd5 dd4 wd1 wd2 wd3 wd4 sd_dqs3/sd_dqs2 dd9 sd_clk dd3 dd2 d[31:24]/d[23:16] wd1 wd2 wd3 wd4 dd10 cl=2 cl=2.5 col dqs read preamble dqs read postamble dqs read preamble dqs read postamble cl = 2.5 cl = 2 sd_clk sd_clk v ix v mp v ix v id
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 34 figure 21. gpio timing 5.9 reset and configurat ion override timing figure 22. reset and configuration override timing notes: 1 gpio spec cover: irq n , uart and timer pins. table 13. reset and configuration override timing num characteristic symbol min max unit r1 reset input valid to fb_clk high t rvch 9?ns r2 fb_clk high to reset input invalid t chri 1.5 ? ns r3 reset input valid time 1 notes: 1 during low power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. t rivt 5?t cyc r4 fb_clk high to rstout valid t chrov ?10ns r5 rstout valid to config. overrides valid t rovcv 0?ns r6 configuration override setup time to rstout invalid t cos 20 ? t cyc r7 configuration override hold time after rstout invalid t coh 0?ns r8 rstout invalid to configuration override high impedance t roicz ?1t cyc g1 fb_clk gpio outputs g2 g3 g4 gpio inputs r1 r2 fb_clk reset rstout r3 r4 r8 r7 r6 r5 configuration overrides*: r4 (rcon , override pins)
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 35 note refer to the MCF5208 reference manual for more information. 5.10 i 2 c input/output timing specifications table 14 and table 15 list specifications for the i 2 c input and output timing parameters. table 14. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 start condition hold time 2 ? t cyc i2 clock low period 8 ? t cyc i3 i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 ? t cyc i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? t cyc i9 stop condition setup time 2 ? t cyc table 15. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units i1 1 notes: 1 note: output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) re sults in minimum output timings as shown in table a-16. the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2c_scl low period. the actual position is affected by the pre scale and division values programmed into the ifdr; however, the numbers given in table a-16 are minimum values. start condition hold time 6 ? t cyc i2 1. clock low period 10 ? t cyc i3 2 2 because i2c_scl and i2c_sda are open-collector-type outputs, which the processor can only actively drive low, the time i2c_scl or i2c_sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ? ? s i4 1. data hold time 7 ? t cyc i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 ns i6 1. clock high time 10 ? t cyc i7 1. data setup time 2 ? t cyc i8 1. start condition setup time (for repeated start condition only) 20 ? t cyc i9 1. stop condition setup time 10 ? t cyc
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 36 figure 23. i 2 c input/output timings 5.11 fast ethernet ac timing specifications mii signals use ttl signal levels compatible with devices operating at either 5.0 v or 3.3 v. 5.11.1 mii receive signal timing (fec_rxd[3:0], fec_rxdv, fec_rxer, and fec_rxclk) the receiver functions correctly up to a fec_rxclk maximum freque ncy of 25 mhz +1%. there is no minimum frequency requirement. in addition, the pr ocessor clock frequency must exceed twice the fec_rxclk frequency. table 16 lists mii receive channel timings. figure 24 shows mii receive sign al timings listed in table 16 . figure 24. mii receive signal timing diagram table 16. mii receive signal timing num characteristic min max unit m1 fec_rxd[3:0], fec_rxdv, fec_rxer to fec_rxclk setup 5? ns m2 fec_rxclk to fec_rxd[3:0], fec_rxdv, fec_rxer hold 5 ? ns m3 fec_rxclk pulse width high 35% 65% fec_rxclk period m4 fec_rxclk pulse width low 35% 65% fec_rxclk period i2 i6 i1 i4 i7 i8 i9 i5 i3 i2c_scl i2c_sda m1 m2 fec_rxclk (input) fec_rxd[3:0] (inputs) fec_rxdv fec_rxer m3 m4
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 37 5.11.2 mii transmit signal timing (fec_txd[3:0], fec_txen, fec_txer, fec_txclk) table 17 lists mii transmit channel timings. the transmitter functions correct ly up to a fec_txclk maximum fr equency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the processor clock fr equency must ex ceed twice the fec_txclk frequency. the transmit outputs (fec_txd[3:0] , fec_txen, fec_txer) can be programmed to transition from either the rising or falli ng edge of fec_txclk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for detail s of this option and how to enable it. figure 25 shows mii transmit si gnal timings listed in table 17 . figure 25. mii transmit signal timing diagram 5.11.3 mii async inputs signal timing (fec_crs and fec_col) table 18 lists mii asynchronous inputs signal timing. figure 26 shows mii asynchronous i nput timings listed in table 18 . table 17. mii transmit signal timing num characteristic min max unit m5 fec_txclk to fec_txd[3: 0], fec_txen, fec_txer invalid 5? ns m6 fec_txclk to fec_txd[3:0], fec_txen, fec_txer valid ? 25 ns m7 fec_txclk pulse width high 35% 65% fec_txclk period m8 fec_txclk pulse width low 35% 65% fec_txclk period table 18. mii async inputs signal timing num characteristic min max unit m9 fec_crs, fec_col minimum pulse width 1.5 ? fec_txclk period m6 fec_txclk (input) fec_txd[3:0] (outputs) fec_txen fec_txer m5 m7 m8
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 38 figure 26. mii async inputs timing diagram 5.11.4 mii serial management channel timing (fec_mdio and fec_mdc) table 19 lists mii serial management channel timings. the fec functio ns correctly with a maximum mdc frequency of 2.5 mhz. figure 27 shows mii serial management channel timings listed in table 19 . figure 27. mii serial management channel timing diagram table 19. mii serial management channel timing num characteristic min max unit m10 fec_mdc falling edge to fec_mdio output invalid (minimum propagation delay) 0? ns m11 fec_mdc falling edge to fec_mdio output valid (max prop delay) ? 25 ns m12 fec_mdio (input) to fec_mdc rising edge setup 10 ? ns m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns m14 fec_mdc pulse width high 40% 60% fec_mdc period m15 fec_mdc pulse width low 40% 60% fec_mdc period fec_crs m9 fec_col m11 fec_mdc (output) fec_mdio (output) m12 m13 fec_mdio (input) m10 m14 m15
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 39 5.12 32-bit timer module ac timing specifications table 20 lists timer module ac timings. 5.13 qspi electrical specifications table 21 lists qspi timings. the values in table 21 correspond to figure 28 . figure 28. qspi timing table 20. timer module ac timing specifications name characteristic unit min max t1 dt0in / dt1in / dt2in / dt3in cycle time 3 ? t cyc t2 dt0in / dt1in / dt2in / dt3in pulse width 1 ? t cyc table 21. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 510 tcyc qs2 qspi_clk high to qspi_dout valid. ? 10 ns qs3 qspi_clk high to qspi_dout invalid. (output hold) 1.5 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 40 5.14 jtag and boundary scan timing figure 29. test clock input timing table 22. jtag and boundary scan timing num characteristics 1 notes: 1 jtag_en is expected to be a static signal. henc e, specific timing is not associated with it. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4? t cyc j3 tclk clock pulse width t jcw 26 ? ns j4 tclk rise and fall times t jcrf 03 ns j5 boundary scan input data setup time to tclk rise t bsdst 4? ns j6 boundary scan input data hold time after tclk rise t bsdht 26 ? ns j7 tclk low to boundary scan output data valid t bsdv 033 ns j8 tclk low to boundary scan output high z t bsdz 033 ns j9 tms, tdi input data setup time to tclk rise t tapbst 4? ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 ? ns j11 tclk low to tdo data valid t tdodv 026 ns j12 tclk low to tdo high z t tdodz 08 ns j13 trst assert time t trstat 100 ? ns j14 trst setup time (negation) to tclk high t trstst 10 ? ns tclk v il v ih j3 j3 j4 j4 j2 (input)
preliminary electrica l characteristics MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 41 figure 30. boundary scan (jtag) timing figure 31. test access port timing figure 32. trst timing 5.15 debug ac timing specifications table 23 lists specifications for the de bug ac timing parameters shown in figure 33 & figure 34 . input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst j14 j13
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary preliminary electrical characteristics freescale semiconductor 42 figure 33 shows real-time trace timing for the values in table 23 . figure 33. real-time trace ac timing figure 34 shows bdm serial port ac timing and bkpt pin timing for the values in table 23 . table 23. debug ac timing specification num characteristic units min max de0 pstclk cycle time ? 0.5 t cyc de1 pst valid to pstclk high 2 ? ns de2 pstclk high to pst invalid 1 ? ns de3 dsclk cycle time 5 ? t cyc de4 dsi valid to dsclk high 1 ? t cyc de5 1 notes: 1 dsclk and dsi are synchronized internally. de4 is measured from the synchronized dsclk input relative to the rising edge of fb_clk. dsclk high to dso invalid 4 ? t cyc de6 bkpt input data setup time to fb_clk high 4 ? ns de7 fb_clk high to bkpt invalid 0 ? ns pstclk pst[3:0] de2 de1 ddata[3:0] de0
revision history MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary freescale semiconductor 43 figure 34. bdm serial port ac timing 6 revision history table 24. revision history revision number date substantive changes 0 5/23/2005 initial release 0.1 6/16/2005 corrected 144qfp pinout in figure 1 . pins 139-142 incorrectly showed fec functionality, which are actually uart 0/1 clear-to-send and request-to-send signals. changed maximum core frequency in ta b l e 8 , spec #2, from 240mhz to 166.67mhz. also, changed symbols in table: f core -> f sys and f sys -> f sys/2 for consistency throughout doc ument and reference manual. dsi dso current next fb_clk past current dsclk de3 bkpt de6 de7 de4 de5
MCF5208 coldfire ? microprocessor data sheet, rev. 0.5 preliminary revision history freescale semiconductor 44 0.2 8/26/2005 changed ball m9 from sd_vdd to evdd in figure 9 . ta b l e 3 : pin 33 for 144 lqfp package should be evdd instead of sd_vdd. be/bwe [3:0] for 144 lqfp should be ?20, 48, 18, 50? instead of ?18, 20, 48, 50? cleaned up various electrical specifications: ta b l e 4 : added ddr/memory pad supply voltage spec, changed ?clock synthesizer supply voltage? to ?pll supply voltage?, changed min pllv dd from -0.5 to -0.3, changed max v in from 4.0 to 3.6, changed minimum t stg from -65 to -55, ta b l e 5 : changed tbd values in t j entry to 105 c. ta b l e 7 : changed minimum core supply voltage from 1.35 to 1.4 and maximum from 1.65 to 1.6, added pll supply voltage entry, added pad supply entries for mobile-ddr, ddr, and sdr, changed minimum input high voltage from 0.7xev dd to 2 and maximum from 3.65 to ev dd +0.05, changed minimum input low voltage from vss-0.3 to -0.05 and maximum from 0.35xev dd to 0.8, added input high/low voltage entries for ddr and mobile-ddr, removed high impedance leakage current entry, changed minimum output high voltage from ev dd -0.5 to ev dd -0.4, added ddr/bus output high/low voltage entries, removed load capacitance and dc injection current entries. added filtering circuits and voltage sequencing sections: section 5.4.1, ?pll power filtering,? and section 5.4.2, ?supply voltage sequencing and separation cautions.? removed ?operating co nditions? table from section 5.5, ?oscillator and pll electrical characteristics,? since it is redundant with ta bl e 7 . ta b l e 9 : changed minimum core frequency to tbd, removed external reference and on-chip pll frequency specs to have only a clkout frequency spec of tbd to 83.33mhz, removed loss of reference frequency and self-clocked mode frequency entries, in extal input high/low voltage entries changed ?all other modes (dual controller (1:1), bypass, external)? to ?all other modes (external, limp)?, removed xtal output high/low voltage entries, removed power-up to lock time entry, removed last 5 entries (frequency un-lock range, frequency lock range, clkout period jitter, frequency modulation range limit, and ico frequency) 0.3 9/07/2005 corrected dramsel footnote #3 in ta b l e 3 . updated ta b l e 3 with 144mapbga pin locations. added 144m apbga ballmap to section 4.3, ?pinout?144 mapbga.? changed j12 from pll_vdd to ivdd in figure 9 . 0.4 10/10/2005 figure 1 and ta bl e 3 : changed pin 33 from evdd to sd_vdd figure 4 and ta bl e 3 : changed ball d10 from test to vss figure 6 and ta b l e 3 : changed pin 39 from evdd to sd_vdd and pin 117 from test to vss 0.5 3/29/2006 added ?top view? and ?bot tom view? labels where appropriate to mechanical drawings and pinouts. updated mechanical drawings to latest available, and added note to section 4, ?mechanicals and pinouts.? table 24. revision history (continued) revision number date substantive changes
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